Predictive Yield Modeling Using Machine Learning and Process Metrology Data in Semiconductor Fabrication

Abstract

Semiconductor fabrication requires high process control because small metrology changes can reduce wafer yield and increase production cost. Predictive yield modeling helps identify yield risk before final electrical testing and supports faster process correction. Existing literature shows that machine learning, virtual metrology, sensor mining, and explainable models can improve yield estimation and root-cause analysis in semiconductor manufacturing. However, many models still treat process variation, defect indicators, and interpretation outputs as separate tasks. This gap limits their practical use for fabrication engineers who need early, clear, and actionable yield-risk information. This article develops a machine-learning framework that uses process metrology data, feature engineering, model comparison, and interpretation outputs to predict wafer yield. The study compares random forest, gradient boosting, support vector machine, and multilayer perceptron models using simulated fabrication-lot data. The results show that gradient boosting provides the strongest prediction performance and supports reliable classification of high-yield, moderate-risk, and low-yield lots.